Implementation analysis of block cipher components and structures

This thesis analyzes the implementation and performance characterization of symmetric key block ciphers. In particular, we study block ciphers which consist of Substitution-boxes (S-boxes) and Maximum Distance Separable (MDS) mappings. New mechanisms are proposed to evaluate the performance of block ciphers in terms of complexity and security for both hardware and software implementations. Configured with parameterized components, many cipher cases are derived from two cipher structures, a nested Substitution-Permutation Network (SPN) and a class of Feistel networks. In our study of each case, the hardware complexity and speed are evaluated by considering a gate network consisting of one- or two-input logic gates, which is suitable for an Application-Specific Integrated Circuit (ASIC) realization. The software complexity (in terms of both speed and memory requirements) is evaluated through table lookup implementations, which is a classical approach used for fast software implementations. The results of the complexity evaluation are verified with implementations using 0.18 μm and 0.35 μm CMOS technologies for hardware and C/C++ compilers for software. Cipher security, in the form of resistance to differential and linear attacks, is used to normalize the performance in the analysis. Because the discussed structures are similar to many existing ciphers such as the Advanced Encryption Standard (AES) and Camellia, this mechanism enables us to study the efficiency of existing and new ciphers through a wide comparison of security, performance, and implementation methods. -- In addition to differential and linear cryptanalysis, we also examine integral, eXtended Sparse Linearization (XSL), and power attacks that may be applied to block ciphers. The XSL attack is discussed with respect to its effectiveness on the various studied cipher structures. Finally, a simple power analysis attack is implemented on Camellia's key schedule in the circumstance where the processor leaks Hamming weight information and the influence of the attack on the design of key schedules is explored