Performance-driven parasitic-aware layout retargeting and optimization for analog and RF integrated circuits

Performance of analog and radio-frequency (RF) integrated circuits is highly sensitive to layout parasitics. Layout-induced parasitics must be optimized to achieve desired circuit performance. This dissertation surveys the previous analog design automation approaches and presents an improved performance-constrained algorithm that can automatically conduct template-based parasitic-aware retargeting and optimization for analog and RF layouts. Piecewise sensitivities are deployed to represent the dependence of performance with respect to layout parasitics. The algorithm then uses these piecewise sensitivities to control parasitic-related layout geometries by directly constructing a set of performance constraints, subject to the maximum allowed performance deviation. Different from previous approaches that only consider parasitic resistances and wire-substrate capacitances, parasitic inductances and wire-coupling capacitances are taken into account to enable successful layout retargeting, in particular when handling RF layouts. The formulated problem is solved using graph-based techniques, combined with mixed-integer nonlinear programming (MINLP). The proposed method is incorporated into a template-based layout design tool called IPRAIL. The proposed algorithm has been demonstrated to be effective and efficient for generating target analog/RF layouts during process migration and/or performance retargeting