Analysis and compilation techniques for HARPO/L

Coarse grained reconfigurable architecture (CGRA) is a reconfigurable architecture that uses word-width processing elements, and provides custom designed reconfigurable datapath units (rDPUs) as basic logic units. It combines some strength of both software and hardware to provide an easy to develop, and highly efficient platform. In this thesis, I make contributions to the development of an object oriented language, HARdware Parallel Object Language (HARPO/L), which is suitable to describe the parallel execution of hardware, and hence can be compiled directly to CGRA platform. -- This thesis will mainly concentrate on the front-end of the HARPO/L compiler, to address technical issues arising from some of the unique characteristics of our language. This thesis will develop a formal mathematical representation for HARPO/L, to help verify the semantics of the language. It will also develop a method to identify synchronization problems in shared variable access, and to simplify the implementation of atomicity in language. Furthermore, in addition to the research work in this thesis, a compiler front-end is also implemented in JAVA to compile the plain text source code to typed abstract syntax tree (AST). We will also discuss some techniques involved in implementing such a compiler front-end