Modeling and optimizing NUMA effects and prefetching with machine learning

Both NUMA thread/data placement and hardware prefetcher configuration have significant impacts on HPC performance. Optimizing both together leads to a large and complex design space that has previously been impractical to explore at runtime. In this work we deliver the performance benefits of optimizing both NUMA thread/data placement and prefetcher configuration at runtime through careful modeling and online profiling. To address the large design space, we propose a prediction model that reduces the amount of input information needed and the complexity of the prediction required. We do so by selecting a subset of performance counters and application configurations that provide the richest profile information as inputs, and by limiting the output predictions to a subset of configurations that cover most of the performance. Our model is robust and can choose near-optimal NUMA+Pre-fetcher configurations for applications from only two profile runs. We further demonstrate how to profile online with low overhead, resulting in a technique that delivers an average of 1.68X performance improvement over a locality-optimized NUMA baseline with all prefetchers enabled.This work has been supported by the European Research Council grant Nos. 715283 and 321253, the Knut and Alice Wallenberg Foundation through the Wallenberg Academy Fellows program (No. 2015.0153), the Spanish Ministry of Economy and Competitiveness (contract TIN2015-65316-P), the European HiPEAC Network of Excellence, and the Generalitat de Catalunya (contracts 2017-SGR-1414 and 2017-SGR-1328). I. Sánchez Barrera has been partially supported by the Spanish Ministry of Education, Culture and Sport under Formación del Profesorado Universitario fellowship number FPU15/03612 and by the Spanish Ministry of Science, Innovation and Universities under Ayudas a la movilidad para estancias breves y traslados temporales fellowship number EST18/00799. M. Casas and M. Moretó have been partially supported by the Spanish Ministry of Economy, Industry and Competitiveness under Ramón y Cajal fellowship numbers RYC-2017-23269 and RYC-2016-21104, respectively.Peer ReviewedPostprint (published version