High speed serial links for on-chip networking

Future technologies will allow the integration of hundreds of billions of transistors on a single chip allowing the fabrication of chips with hundreds of processing cores. So, IC designers should focus on the communication between these cores in order to meet the design requirements in terms of speed, area, power consumption, and time to market constraints. Using conventional parallel buses to transmit data on-chip is not efficient anymore in terms of area, given that in new technologies interconnects do not scale at the same rate as transistors do, and in terms of power due to the large number of drivers, repeaters, and buffers. Also, parallel buses suffer from timing errors due to jitter, and cross talk that eventually limit the performance. One of the solutions to solve these on-chip communication issues is to replace conventional parallel buses with serial links. Although serial communication for both on-chip and off-chip look similar, different problems are faced while designing each of them, leading to different design requirements. Many publications already proposed solutions based on serial links, and dealt with the inter symbol interference on their interconnects using equalization, frequency translation using high frequency carrier signal or using data encoding, or using resistive terminated interconnects. This thesis discusses the on-chip interconnect characteristics, and the difference between them and their off-chip counterparts. Based on their characteristics, the design problems of on-chip interconnects are identified, and solutions are proposed. The thesis proposes a new architecture that multiplexes both data and clock on serial links, reduces inter symbol interference by using a resistive termination technique, and uses two-level Manchester encoding to solve the reduced swing problem and enable the use of power efficient circuitry. Using this signaling scheme makes the system jitter insensitive, and avoids the need for a power hungry clock and data recovery circuit. A self-calibrating digital-delay line is also implemented inside the decoder to enable the system to operate efficiently across process, voltage and temperature variations. The proposed architecture is prepared to be fabricated using the UMC 0.13um CMOS technology. Finally, the proposed system\u27s testing challenges are discussed, and an on-chip testing setup is proposed so that the system meets the design for testability requirements to facilitate the system testing after fabrication. The testing setup is designed for the previously mentioned tape-out, and for another tape-out using the GF 65nm CMOS technology