Development of Communication Protocols on FPGA through PCIe

The research project I am proposing is an extension of a previous Texas A&M Senior Design Project completed in the spring of 2019 by four students. Their project was to develop protocols on FPGA through the use of PCIe. Their main areas of focus were on increasing bandwidth by aggregating PCIe lanes, reducing latency on performance critical accelerators and matching current PCIe transfer rate. My research will go even further with their project. I will take their previous design and streamline its features, improve performance mechanics and most importantly implement the package onto an FPGA. This purpose behind this project is to create a faster and higher performing PCIe protocol for data transfers, a key component in the large industry of data management and storage. The goals of this research project are to increase performance, decrease latency and improve the design of the previous project and implement it all on an FPGA board