Temperature Sensitivity in Mos Operational Amplifiers.

The objective of this study was to investigate the temperature drift mechanisms in NMOS operational amplifiers. This research has concentrated on underst and ing these mechanisms over a temperature range of -50(DEGREES)C to +100(DEGREES)C. An amplifier was designed and fabricated to serve as a test vehicle for the temperature studies. The silicon-gate enhancement-only amplifier, optimized to dissipate only 3.8 mW at (+OR-)10 V, nevertheless produces a voltage gain of 200 and a unity-gain b and width of 600kHz. Three sources of temperature drift are identified: threshold voltage, inversion layer mobility, and junction leakage current. An improved SPICE model is developed for the threshold voltage temperature coefficient. This model takes into account the temperature dependence of the fast surface state charge. The measured zero-bias threshold voltage temperature coefficient was typically -4.1 mV/(DEGREES)C. A new SPICE model is also developed for the junction leakage current, modeling it as a generation current with a temperature dependence proportional to the intrinsic carrier concentration and a voltage dependence proportional to the square root of the reverse-biased junction voltage. Good agreement between these new SPICE models and the experimental results is shown. For the present amplifier design, the offset voltage drift is shown to be isolated in the differential input stage due to threshold voltage drift cancellation between the differential-to-single-ended converter stage and the subsequent inverter stage. This is shown analytically and has been confirmed with SPICE using the new temperature models. To a first order approximation, the offset voltage drift represents a mismatch in the threshold voltage temperature coefficients of the input transistors in the differential input stage. Neglecting junction leakage current, the measured offset voltage drift for this amplifier was typically 30 (mu)V/(DEGREES)C, among the lowest values ever reported for an MOS amplifier. With the improved SPICE temperature models, it is shown that the room-temperature junction leakage current density must be maintained below 10 nA/cm('2) to have a negligible effect on the offset voltage drift for temperatures below 100(DEGREES)C. New methods to further reduce the offset voltage and offset voltage drift using circuit techniques are proposed. These involve a commutating offset memorization technique using a two-phase clock and an offset null technique, controlling the back-gate bias of the input transistors in the differential input stage.PhDElectrical engineeringUniversity of Michiganhttp://deepblue.lib.umich.edu/bitstream/2027.42/159343/1/8314242.pd