Design of a Duty-Cycled Fractional-N ADPLL Based on Instantaneous Start-up LC DCO and High-precision DTCs

This thesis deals with the design of a duty-cycled, fractional-N and low-noise Phase Locked Loop (PLL) used for Ultra-Wideband applications in 40 nm process. This is the first-ever Duty-Cycled PLL (DCPLL) that is designed with an LC oscillator and brings down the noise record for DCPLLs by more than 1 order of magnitude. Due to the special architecture used in this design, the DCPLL presented in this thesis can support fractional-N operation without difficulty and achieve a much better fractional-N resolution than its ring oscillator counterpart while requiring little additional hardware and power cost. Furthermore, the latest All-Digital PLL (ADPLL) architecture and techniques are mapped and tailored for this first-ever LC oscillator based Duty-Cycled All-Digital PLL (DC-ADPLL). The performance of this DC-ADPLL is verified by Verilog-AMS simulations.MicroelectronicsElectrical Engineering, Mathematics and Computer Scienc