Measurement and Analysis of Digitally Controlled Oscillator With Pseudo Random Control

[[abstract]]本篇論文是以鎖相迴路裡面的重要元件-數位控制振盪器(DCO)為主要研究對象。透過結合小數控制訊號可以提升數位控制振盪器的解析度，在輸出主頻的偏移量與計算出的預計偏移量結果誤差低於0 01%以下。由於使用週期性小數訊號調控數位控制振盪器會發現在主頻周圍產生週期性的突刺，在本論文針對在降低突刺使用虛擬隨機存儲裝置與無記憶體虛擬隨機亂數兩種技術實測各種不同控制位元抑制週期性突刺並加以分析。 第二章與第三章主要探討低頻域與高頻域DCO使用虛擬隨機存儲裝置調控DCO，在小數控制位元產生的突刺在低頻域輸出224 699MHz之SFDR可由19 7dBm升至47 3dBm提升了27 6dBm，且在高頻域DCO輸出頻率400 89MHz之SFDR由32dBm升至35 8dBm也有改善3 8dBm。並比較三種參考頻率進行量測分析。 於第四章使用無記憶體虛擬隨機亂數量測觀測後發現在小數0 5能更有效打散小數週期降低突刺，在DCO操作在參考頻率20MHz輸出頻率225 337MHz使用無記憶體虛擬隨機亂數比虛擬隨機存儲裝置更提高了35 9dBm，且不受參考頻率影響消除突刺的特性，並降低在實際電路使用上所耗佔的空間。[[abstract]]The research topic of this thesis which is an important component of all-digital phase locked loop (PLL) is digitally controlled oscillator (DCO) It combines the fractional control signal to enhance the resolution of DCO The output frequency offset is under 0 01% The fractional spur will be generated when fractional control signal with periodically This thesis uses two fractional random generators to reduce the fractional spur One is pseudo random generator with memory Another random generator is memory less Chapter two and three investigates the fractional random number with storage for both low frequency DCO and high frequency DCO The SFDR is enhanced from 19 7dBm to 47 3dBm with improvement of 27 6 dBm at 224 699 MHz And the SFDR is improved 3 8dBm at 400 89 MHz We use three reference frequencies to modulate the fractional control signals and measure the output frequency’s performance In chapter four a pseudo random generator without storage is presented The memory less has good spur reduction when fractional control signal is 0 5 When the reference frequency is 20 MHz and the DCO output at 225 33MHz the proposed method can enhance SFDR with 35 dBm The proposed memory less random number generator can greatly reduce the cost and reduction of spu