The Research of Pseudo Random Storage's Application

[[abstract]]摘要 本論文探討線性回授移位暫存器只能產生2N-1個狀態值的缺點，將其缺點改善並且應用到Liming Xiu提出的虛擬隨機存儲裝置來改善因小數位累加溢位值具有週期性而導致的分數突刺，並且與兩組電路架構做結合。 論文第二章將該裝置應用於數位控制振盪器的調控藉由輸入非週期性的溢位值到控制字元來提高數位控制振盪器的頻率輸出解析度，設定一組控制字元並且只對最低位元做改變其頻率輸出分別為425MHz以及430MHz，經調控後輸出頻率為427 5MHz明顯提高了輸出頻率的解析度，在並使用台積電0 18μm製程實現，佈局電路的核心面積為341 34×200 495μm2，採用28Pin之ESD保護電路，整體晶片面積為1024×1024μm2。 論文第三章該裝置也與傳統型飛加器頻率合成器做結合，使用FPGA加以實現飛機器頻率合成器具虛擬隨機存儲裝置以及分析在不同控制字元下抑制分數突刺的效果，在控制字元為15 875輸出頻率為58 861MHz時，其SFDR為54 165dB比傳統型飛加器頻率合成器的SFDR還高出25 003dB，使用台積電0 18μm製程實現，佈局電路的核心面積為357 605×250 235μm2，採用28Pin之ESD保護電路，整體晶片面積為1024×1024μm2。 論文最後由於當線性回授移位暫存器所需的位元數愈高，虛擬隨機存儲裝置所需的位址記憶體組就愈多，導致電路會過於龐大，所以本論文提出一種無記憶體隨機亂數裝置的電路架構來代替虛擬隨機存儲裝置，將其架構與傳統型飛加器頻率合成器做結合並且使用FPGA實現在不同控制字元下抑制分數突刺的驗證與分析，在控制字元為7 5輸出頻率為125 95MHz，其SFDR為32 729dB比傳統型飛加器頻率合成器的SFDR還高出14 537dB，使用台積電0 18μm製程實現，佈局電路的核心面積為344 69×250 235μm2，採用28Pin之ESD保護電路，整體晶片面積為1024×1024μm2。[[abstract]]The Research of Pseudo Random Storage’s Application Student：Da-Cheng Li Advisors：Dr Pao-Lung Chen Department of Computer and Communication Engineering National Kaohsiung First University of Science and Technology Kaohsiung Taiwan R O C Abstract This thesis investigates the drawback of linear feedback shift register (LFSR) which generates only 2N-1 states We improved the problem of LFSR and applied in Liming Xiu’s storage randomization to solve the fractional spur in flying-adder frequency synthesizer We combined the improved LFSR and flying-adder circuits Chapter two applied the proposed LFSR mechanism to improve the resolution digitally controlled oscillator (DCO) We set the frequency control word and the change lowest significant bit (LSB) of DCO The output frequency is 425 MHz and 430 MHz with different inputs The output frequency is 427 5 MHz when the improved LFSR is applied The chip was fabricated in TSMC 0 18 μm process and the chip area is 341 μm x 200 495 μm The test chip has 28 pins and the total area is 1024 μm x 1024 μ m Chapter three applied the improved LFSR with conventional flying-adder frequency synthesizer In addition we use the FPGA to implement the improved LFSR to measure the spur in flying-adder frequency synthesizer In frequency control word is 15 875 the output frequency is 58 861 MHz The spurious-free dynamic range (SFDR) is 54 165 dB which has 25 003 dB better than conventional flying-adder frequency synthesizer The chip was fabricated in TSMC 0 18 μm process and the chip area is 357 6 μm x 250 μm The test chip has 28 pins and the total area is 1024 μm x 1024 μ m Finally we solve the problem that the storage randomization It requires large memory We propose a memory less structure for randomization of fractional spur in flying-adder frequency synthesizer We use the FPGA to measure the spur and verify the function In frequency control word is 7 5 the output frequency is 125 95 MHz The spurious-free dynamic range (SFDR) is 32 79 dB which has 14 53 dB better than conventional flying-adder frequency synthesizer The chip was fabricated in TSMC 0 18 μm process and the chip area is 344 69 μm x 250 235 μm The test chip has 28 pins and the total area is 1024 μm x 1024 μ