Research of Chaotic Circuits Theory in Integrated Circuit

[[abstract]]本論文的研究是關於以蔡氏電路(Chua’s Circuits)為基礎，在積體電路的環境實現相關的架構。除了分析及模擬典型的蔡氏電路外，也將蔡式電路的非線性電阻使用憶阻器來取代。透過模擬軟體Virtuoso、Laker及HSpice，對電路模擬分析各狀態下的電壓、電流波形，討論其所產生的信號特徵。比較由Virtuoso所產生的Netlist在HSpice的波形、Laker產生的Netlist在HSpice的波形以及晶片的量測，本文主要內容如下：第二章介紹在積體電路的環境下關於被動元件其組成架構。使用”0.18um 1.8V/3.3V 1P6M Virtual Mixed Mode/RFCMOS Process”的製程來實作電阻器、電容器、電感器以及二極體，說明其架構組成及基本特性分析。在第三章，介紹蔡氏電路的基本構造與電路方程式。使用NMOS組成無穩態的震盪器，完成電路的前後模擬。而第四章則延續第三章的架構，目的是把第三章所用到的非線性負電阻改用憶阻器取而代之。接著是探討此憶阻器的組成，分別是用運算放大器(OPA)，乘法器(Multiplier)配合適當比例的電阻器和電容器而成。探討運算放大器(OPA)，此運算放大器由2-stage CMOS實現，探討乘法器(Multiplier)，最後為整體架構的實測和晶片實測。[[abstract]]This thesis tries to implement the Chua’s circuit in the environment of the integrated circuit with TSMC 0.18um CMOS process. We perform the analysis and simulation of Chua's circuit. We also use the memristor to replace the nonlinear resistance of Chua's circuit. We perform the simulations voltage and current waveforms to investigate the Chua’s circuit characteristics by using simulation software tools, such as Virtuoso, Laker and HSpice. Finally, we compare the results with chip measurements.?The main contents of this paper are as follows: The second chapter describes the architecture of passive components in integrated circuit environment using "0.18um 1.8V/3.3V 1P6M Virtual Mixed Mode/RFCMOS" process. We implement the resistor, the capacitor, the inductor and diode. We explain the composition of those passive components and their basic characteristics. The third chapter describes the basic structure of the Chua's circuit and circuit equations. We implement the NMOS to form astable oscillator. We finish the pre-simulation and post-simulation. In addition, the chip results are measured. In chapter four, we use the Chau’s circuit in chapter 3. But, the nonlinear negative resistance in chapter is replaced with memristor. Then, we explore the memristor circuit. It consists with the operational amplifier (OPA), the multiplier, in addition with the appropriate ratio of resistors and capacitors. We design the operational amplifier with two-stage structure in CMOS. We also design the multiplier. Finally, measurements results are performed