Research on Wide-Band Delay Locked Loop Based on Interpolated Flying-Adder

[[abstract]]飛加器(Flying-Adder)的結構看起來相當簡潔，然而有正迴授路徑其數學上理論 基礎相當的艱深難懂，原始發明人Liming Xiu 也將出書將其應用推廣，美日及台灣 的廠商也都有投入在頻率的合成應用上。然而要將其應用在全數位延遲鎖定迴路 (All-Digital Delay Lock loop)上，對飛加器(Flying-Adder)所需要的多相位信號做相位間 校準的研究相當少，同時相位間的差異對整體效能的研究也不多見。 本計畫構想是以內插式飛加器(Interpolated Flying-Adder)為基礎之延遲迴路的 設計， 進而探討其相關特性及其應用。也研究校準電路對於內插式飛加器 (Interpolated Flying-Adder)為基礎之延遲迴路的影響，同時研究多相位間信號間 (Multiphase signal)差異造成的影響，也將研究多相位校正的方式。預計其達成的規 格如下:T-18(0.18um)，輸入頻率: 5 MHz ~ 2 GHz， 晶片面積小於1000um x 1000um ，功率消耗在40 mw @ 2 GHz， 鎖定時間小於10 cycles。[[abstract]]The structure of Flying-Adder is very compact for frequency synthesis. Due to the positive feedback, the mathematical formula is very difficult to understand. The inventor of Flying-Adder, Liming Xiu, will publish a textbook to explain the theory of Flying-Adder. Many countries have research on Flying-Adder including USA, Japan and Taiwan. However, there is no research on the application of all-digital delay locked loop as well the impact of phase difference of multiphase signals. The phase calibration algorithm is also very important to the performance of Flying-Adder . This project is to apply our proposed interpolated Flying-Adder into all-digital delay locked loop. We will research the related applications and basic characteristics. We will investigate the impact of phase difference on our proposed interpolated Flying-Adder structure. A new algorithm for calibration will be proposed. We will use TSMC-0.18um process to implement the chip. The target of the chip is that the input frequency will be 5 MHz ~ 2GHz. And, the power consumption is under 40mW and locking time < 10 clock cycles.[[note]]NSC101-2221-E327-04