Design of CMOS Coherent Quadrature Demodulator and Low Noise Frequency Synthesizer for 4G Systems

[[abstract]]本論文提出運用次諧波技術之頻率合成器。相較於傳統式頻率合成器，除頻器不僅帶來相當大的功率消耗，迴路頻寬內也存在著20logN雜訊增益，主導著迴路頻寬內之雜訊表現。次諧波頻率合成器在不使用除頻器情況下完成頻率之合成，因此，達到低相位雜訊與低功率消耗之要求。並使用TSMC 0 18um COMS製程完成次諧波頻率合成器晶片設計。研究結果其迴路頻寬內之相位雜訊在距離載波10kHz之頻率偏移時為-99 49dBc/Hz。 使用TSMC 0 18um COMS製程設計正交同調解調器，正交頻率合成器之相位雜訊在距離載波1MHz頻率偏移時為-96 91dBc/Hz，在3GHz時上鎖與下鎖時間分別為24 8us與26us。並將其整合QPSK數位解調。 使用TSMC 0 18um CMOS 製程設計應用於第四代行動通訊之低雜訊頻率合成器。晶片頻段設計於5 3GHz~5 83GHz，中心頻率為5 565GHz並且可調範圍為530MHz。相位雜訊於距離載波1MHz頻率偏移時為-101 47dBc/Hz。[[abstract]]This paper proposes a Sub-harmonic technology designs a frequency synthesizer Compared with the classical frequency synthesizer the frequency divider dominates the in-band phase noise which not only have great power consumption in system but also have 20logN the gain of noise in in-band The Sub-harmonic frequency synthesizer no frequency divider is needed in locked state Hence divider noise and power can be eliminated The frequency synthesizer is in implemented in TSMC 0 18-um CMOS process the in-band phase noise at 10kHz offset is measured to be -99 49dBc/Hz Designs of coherent quadrature demodulator by TSMC 0 18-um CMOS process The phase noise at 1MHz offset is measured to be -96 91dBc/Hz When the carrier frequency at 3GHz hop to 3 02GHz the locked time is 24us And the carrier frequency at 3 02GHz hopping to 3GHz the locked time is 26us Finally it could combine the quadrature demodulator with QPSK digital demodulation Design a low noise frequency synthesizer for 4G by TSMC 0 18um CMOS process This chip frequency band design in 5 3GHz~5 83GHz This chip has a measured center frequency of 5 565GHz and tuning range of 530MHz The phase noise at 1MHz offset is measured to be -101 47dBc/H