Low Cost Design of FIR Filter Using Curve Fitting Methods

[[abstract]]在本論文裡，我們提出能夠有效化簡面積之有限脈衝響應濾波器(Finite Impulse Response Filter FIR Filter)設計，其中包括針對濾波器之係數及針對濾波器架構化簡，並將提出之係數化簡方法搭配提出之架構，達到更好的化簡效果。 針對濾波器係數化簡部份，我們以面積精簡為主要目的。我們提出四種化簡方法分別為係數映對法、斜率法、係數重排法及改良式係數重排法。而四種化簡方法之運算步驟為量化係數、輸入參數、用參數構成主要係數及用主要係數構成剩餘係數。將係數量化後，利用上述四種化簡方法，以輸入參數方式找出主要係數，之後利用主要係數構成剩餘係數，並計算誤差；在此我們不做任何誤差補償，我們測試所有參數組合，經過驗證及數值統計後，找出在可接受誤差下之最好結果以精簡濾波器面積。 針對濾波器架構化簡部份，同樣以面積精簡為目的。我們提出多工器架構去取代原始架構；相較於原始架構，多工器架構以多工器及回授加法器取代大量暫存器及加法器，如此一來可節省許多電路面積。唯多工器構成係數方式為一個時脈週期構成係數之一部份，故構成一筆係數將耗費數個時脈週期。在此，我們將上述提出之係數化簡方法套入此多工器架構後，找出在可接受誤差且構成係數耗費最短時脈週期下之最好結果，進一步精簡濾波器電路面積。 我們將上述提出之濾波器係數及架構化簡法應用於ITU-T G 729A的80階、240階及IS95 CDMA的48階FIR濾波器上，以輸入為16-bit的架構為例，在不同架構(原始架構與提出之架構)、不同係數表示式(二進制與標準有號數字表示法(Canonic Signed Digit CSD))及不同參數下找出最好結果。根據實驗結果顯示，相較於原始係數及文獻提出之化簡方法，我們提出之化簡方法搭配提出之架構能顯著地改善面積，在Throughput/Area亦有很好的表現。[[abstract]]In this thesis we propose two technologies to reduce the area cost of Finite Impulse Response (FIR) filter design by optimizing it’s coefficients and architecture For the optimization of coefficients we propose four area reduction methods including Mapping Method Slope Method Re-order Method and Modified Re-order Method In these four methods there are four common operation steps including the quantization of coefficients the input of parameters the selection of prime coefficients and the composition of residual coefficients Through performing these steps all coefficients can be generated by the prime coefficients and the needs of arithmetic units in FIR filter are also reduced In this case we will not perform any error compensation here but we will test all input parameters and find the best optimization result by numerical statistics in an acceptable error rate of frequency response For the optimization of architecture we propose a multiplexer-based (MUX) architecture to replace original architecture The MUX-based architecture uses MUXs and feedback adders to replace large numbers of registers and adders in original filter architecture for saving more area cost in realization This design spends about three clock cycles to perform a constant multiplication rather than one clock cycle in original architecture Hence it will sacrifice the throughput of filter to obtain the area cost reduction in an acceptable performance requirement We apply the above coefficient and architecture optimization methods in realizing 80- 240-tap FIR filters of ITU-T G 729A voice protocol and 48-tap filter of IS95 Code-Division Multiple Access (CDMA) communication protocol We also use two different expressions of coefficients including binary and Canonic Signed Digit (CSD) formats for comaring their performances The experimental results show that our two optimization technologies can reduce the area cost of filter design significantly compared with previous designs especially the combination of them can achieve more effect