A Study of Simplified Parallel Variable-Length BCH Encoder

[[abstract]]多層單元（Multi-Level Cell，MLC） 快閃記憶體由於資料錯誤率較高，使得穩定資料的可靠度成為一個重要的議題。使用錯誤更正編碼Error Correction Code (ECC)技術能有效解決此問題，其中BCH碼為常用的錯誤更正碼。 傳統的BCH碼編碼器都以Linear feedback shift register (LFSR)架構來實現。LFSR是序列編碼方式，一次只能處理一個位元，若編碼長度較長將會有fan-out問題；平行LFSR架構能解決此問題但需增加硬體成本。本論文提出的可變長度BCH碼平行編碼是藉由研究LFSR運算規則而推導出一通用運算式，此運算式能計算出第n個訊息位元進入時，暫存器內的值是由哪幾個訊息位元做xor運算而來，藉由此運算式結果來實現平行 BCH編碼，此方法能有效減少平行編碼所需的邏輯閘的數量。 實驗部分是使用Xilinx ISE合成報告來模擬本論文方法和傳統平行BCH編碼所需的邏輯閘數目，並發現本論文方法在越長的編碼上節省的的邏輯閘數目越多。[[abstract]]Given the high demand of mass storage Multi-level cell (MLC) flash memory has developed rapidly However due to the MLC flash memory data error rate is high how to maintain the reliability of the information has become an important issue Nowadays error correction code (ECC) technology is quite a mature technology In this work we focus on the Bose-Chaudhuri-Hocquenghem (BCH) codes Traditional BCH code encoder was implemented by using Linear Feedback Shift Register (LFSR) structure However the LFSR architectures need to address the effect of large fan-out in the case of long massage length To this end this work proposes the parallel BCH codes encoder for variable length by studying the LFSR calculation rules Comparing with other methods the proposed method can effectively reduce the hardware cost The simulation is conducted under the Xilinx platfor