H.264/AVC Intra-Frame Codec Design and Real-Time FPGA Implementation

[[abstract]]在這篇論文中，我們設計一個H.264/AVC內在圖框之編解碼器，並以ALTERA之DE2-70實現即時視訊之編解碼動作。編解碼器之工作頻率為50MHz。編碼器使用了5632(Logic Elements)。解碼器使用2938(Logic Elements)。數位相機(MT9M011)所擷取的即時視訊之大小為320 256 15(Frame/Sec)。在解碼器與TFT-LCD(TPG051)間的溝通介面，我們設計一個SSRAM(IS61LPS51236A)的控制模組，用來控制並儲存解碼器所解回之即時影像於SSRAM中，以待TFT-LCD模組的讀取。在整個FPGA系統上，我們設計一個編解碼器的控制單元，以控制H.264/AVC之編解碼器。編碼器的壓縮效率，當QP=16時，視訊的壓縮率平均可達11倍，於平滑畫面，平均壓縮率更可高達23倍。本論文所設計的CAVLC編解碼器之硬體架構，於Coeff_token、T1_sign、Level、TotalZeros、RunBefore部分，皆以查表法完成。除Level使用JVT-C028標準外，其餘皆符合H.264/AVC之標準。[[abstract]]In this thesis, we design a real time H.264/AVC Intra-Frame codec. The main function includes intra-prediction (vertical mode), transform, quantization, and CAVLC coding. ALTERA DE2-70 development system is used to verify the IP code of encoder and decoder in real-time video coding operation. As mapping to FGPA chip, the operating frequency can work on 50MHz. The size of encoder and decoder is 5632 and 2938 Logic Elements, respectively. Digital camera (MT9M011) is used to catch 320 256 15 (Frame/Sec) real-time videos. And then the video is coded with encoding process in encoder core. The compressed bit-stream is sent to the decoder for displaying decoding videos. For this, we control the TFT-LCD (TPG051) interface with the design a SSRAM (IS61LPS51236A) control module for data access. For real-time encoding and decoding, we design a codec control unit to control the timing schedule for H.264/AVC codec. In experiments, when QP = 16, the video compression ratio can be up to 11 times in average. Even for the smooth screen, the averaged compression ratio can be up to 23 times