High Accurate Quarter-Pixel Motion Estimation Algorithm and VLSI Architecture Implementation for H 264/AVC

[[abstract]]在近年來，數位多媒體的發展迅速使得影像傳輸品質的要求越來越高，不只傳輸速度要快，而且視訊畫面的品質也要有一定的水準。伴隨的卻是傳輸資料量越來越大，為此H.264/AVC視訊壓縮標準已發展而出，它提供了比舊有壓縮技術更佳的編碼效能。在H.264/AVC中採用了更複雜的編碼方式，包括參考畫面可多達五張與可變區塊移動估測，而且非整數像素移動估測則可達到四分之ㄧ像素的精確度，以提供更好的視訊品質與更低的位元率。 在本論文中，我們採用二階式做法。在第一步，移動估測搜尋整數像素點並且找到最小誤差區塊與最佳移動向量的位置，然後此位置將成為下一步搜尋的中心點並設定搜尋範圍為-2~1.75。在第二步，演算法將先內插1/4像素，接著以全域搜尋進行非整像素移動估測。硬體架構設計則分為三個主要部份:整數像素搜尋、1/4像素內插與1/4像素搜尋。為了有效使用硬體架構，每一部份皆在400個時脈內完成。使用Xilinx ISE9.2i工作平台，合成閘數為316.2K、最大工作頻率159.77 MHz。[[abstract]]H.264/AVC coder of the video compression standard has already been developed, it can provide better coding efficiently than previous other techniques. For better motion compensation, the motion estimation used five reference frames and variable block-size, as well as quarter-pixel of the accuracy. In this thesis, we design efficient quarter-pixel estimation in both algorithm level and architecture level. The search process is split to two-step procedures. In the first step, the motion estimation searches the integer-pixel and finds the position of the minimum SAD and best MV. Then we move the searching position to the best MV as the central vector for the next search step. In the second step, the algorithm first will interpolate the quarter-pixels, then carrying on the fractional motion estimation by the full search with the range of -2~1.75. In software simulation, the computational cost can be greatly reduced compared to the original quarter-pixel full search when achieving about 2dB gain to integer search. VLSI architecture is developed for real-time interpolation with the operator saving process. With pipelined scheduling, one MB can be finished in 400 cycles. The gate count is 230k and the maximum frequency can achieve 27.9MHz with the Xilinx ISE9.2i Working platform