Fast Variable Block-Size Motion Estimation Algorithm and Hardware Implementation for H 264

[[abstract]]近來年發展的H.264/AVC提供了較以往編碼演算法更好的視覺品質，但其移動估測與16×16到4×4的模式決策方式花費複雜的編碼計算。為了簡化硬體實現的複雜度，本論文發展出九宮格移動估測演算法，並加上快速區塊決策演算法與動態調整的門檻值以配合不同的視訊序列。在JM8.6的測試中，本論文的演算法表現出不錯的視訊品質，在較為動態的視訊序列當中只降低了0.04到0.09dB，也減少了90%以上的估測時間。硬體設計方面，本論文將巨區塊切割成16個4×4子區塊進行九宮格移動估測，硬體架構為：一個PE陣列一次處理4對像素、一個LPE模組包含了3個PE陣列、8組LPE用來計算移動估測。我們提出了提早預測估測方向的機制，我們可以在256時脈內完成搜尋範圍±16的估測，最後使用合併的方式計算出41種SAD值。硬體可達到100%的PE利用率。使用TSMC 0.18um製程，合成閘數為230K、最大工作頻率27.9MHz[[abstract]]H.264/AVC coder can offer a better visual quality than the previous coding standards. It can achieve better motion-compensation with variable block size coding from 4×4 to 16×16. However, the complexity is high since there are 41 motion vectors to be computed for one MB block. First, we propose a fast algorithm that consists of fast 9-Postion ME and mode decision algorithm with dynamic thresholds to reduce the complexity of motion estimation (ME) for various coding modes. Simulations show that our proposed algorithm can save 90% searching time under H.264 program JM8.6 while PSNR only decreases about 0.05dB. For real-time implementation, we develop parallel architecture and the pipelined schedule based on the proposed algorithm. Our hardware resources uses 96 PE as a basic PE(BPE) processing 4 PE, a LPE module containing 3 BPE arrays, and there are 8 LPE modules employed in parallel. We could can achieve 41 SAD values for each motion mode within 256 cycles when the search range is ±16. The hardware efficiency is 100% PE utilization. The gate count is 230k and the maximum frequency can achieve 27.9MHz with the TSMC 0.18um process