A 2D FPGA-based clustering algorithm for the LHCb silicon pixel detector running at 30 MHz

Starting from the next LHC run, the upgraded LHCb data acquisition system will read and process events at the full LHC collision rate (averaging 30 MHz) by means of a large CPU farm. In order to save the power and flexibility of CPUs for the higher level tasks, an effort is being made to address the lowest-level, more repetitive tasks at the earliest stages of the data acquisition, by means of specialized processors, generally called “accelerators”. Modern FPGA devices are very well-suited to perform with a high degree of parallelism certain computations, that would be significantly time demanding if performed on general-purpose CPUs. This thesis describes a custom firmware implementation of a new 2D cluster-finder algorithm for the LHCb VELO pixel detector, that will run in the LHCb FPGA readout cards in real time during data taking at the unprecedented event rate of 30 MHz. The results and the performances achieved with this specialized system are reported after being measured in tests emulating realistic running conditions of the LHCb Upgrade and the operation of the clustering algorithm at low level