Low power dual stack in mtcmos circuits using dynamic logic and sleep transistor techniques

The demand of delivering faster, smaller, and highly reliable integrated circuit chips is what drives the semiconductor market. The most crucial design parameter that requires ultimate attention is power consumption. In the chip design, it is very important to consider the factors of power dissipation, operating speed and area. In this paper, the dual stack flip flop circuit is designed in sleep transistor method, dynamic CMOS logic method and pass transistor logic (PTL). The dual stack technique is compared in terms of power area, frequency, dissipation, final voltage and maximum Idd current with sleep transistor method, dynamic logic and PTL logic. The proposed dual stack sleep transistor technique that has reduced leakage power, decreased area among the three logics. The circuit is simulated by DSCH2 CAD tool and layouts are generated by micro wind CAD tools. The circuits are simulated in CMOS 0.12μm technology at 1.2V