Virtual Single-Core for Multicore Real-Time Computing

This paper introduces Virtual Single-Core (VSC) technology that allows engineers to use a group of cores in a multicore computer as if the group of cores were a larger single-core computer. Multicore technology has many benefits, such as increased CPU bandwidth per chip. However, when used as is, inter-core interferences can be severe. Because of the potential for large and random delay spikes, the U.S. Federal Aviation Administration (FAA), European Aviation Safety Agency (EASA), and Transport Canada specify that only one core can be used, unless inter-core interference is specifically defined and handled. In addition, DO-178C: Software Considerations in Airborne Systems and Equipment Certification is for single-core chips only. Single-core Equivalence (SCE) technology partitions the resources shared by cores in such a way that each core can be used as if it were a single-core computer. SCE is an effective solution that address certification authorities' concerns of intercore interference. However, a core in a multicore chip is often slower than a fast single-core chip. Therefore, a large multi-thread (task) application may not be scheduled within a core. Virtual Single-Core (VSC) technology extends the SCE technology so that a group of cores can be used to schedule a large application as if the VSC were a larger single-core computer. VSC greatly facilities the migration of certified avionics software from single-core computers to multicore computers.This work was supported in part by Office of Naval Research N00014-17-1-2783, by National Science Foundation CNS 1302563, The views expressed here are those of the authors and do not represent the views of the sponsors.Ope