BUILDING CUSTOMIZED RISC-V SOC WITH SYSTOLIC ARRAY OPTIMIZED FOR SPECIALIZED MATRIX MULTIPLICATION

With diminishing performance improvement from general-purpose processors and reducing cost for programmable hardware, accelerating computation with dedicated accelerators has been gaining increased attention, with FPGAs as a widely preferred choice. However, due to the absence of a generic platform and the lack of abstraction, the costly and challenging development process is a significant problem. Numerous efforts have been made into making the development of hardware systems an easier and more manageable task. In this paper, we will examine the emerging tools, frameworks, and platforms that aim to simplify the process of designing, implementing, and testing of hardware acceleration systems. In particular, we will go through the implementation of a hardware accelerator that boosts a unique form matrix multiplication, which involves a weight matrix sampled from a probabilistic distribution. We will demonstrate how it is possible to modify existing RISC-V based SoC designs into supporting the type of algorithm we desire. The accelerator is written in Chisel, and based on the Rocket Chip and Gemmini from the Chipyard Framework. AWS FPGA is used to synthesize and deploy the design. In the appendix, we also introduce a design of a shim which integrated the accelerator into real-world systemsU of I OnlySenior thesis not recommended for open acces