FOpenCL: An optimized OpenCL-to-FPGA design flow for Xilinx SDx

The semiconductor industry has been working constantly to reduce transistor size and thereby to get the last bit of performance out of single-core processors. With miniaturization becoming more difficult due to the physical limit and fabrication technique limit, alternative techniques to increase computing performance, like parallelism, have become more popular. GPU and FPGA are two significant examples of accelerators that provide high-degree parallelism and can yield significant speed-up if the developer properly understands the parallelism. However, in reality, it is very difficult to explore all the fine and coarse grained parallelism in the specific applications. Previous work has explored the adaptation of CUDA code to FPGA synthesizable C code. In our work, we discover and explain why OpenCL kernels designed for GPU will have poor performance on FPGA if the kernels are copied over without transformation and optimization. Specifically, we uncover an implicit limitation in Xilinx SDx, which claims to support OpenCL. Then, we explore the possibility of transforming OpenCL kernels to achieve better performance and hardware usage on FPGAs. Our proposed FOpenCL flow works around the limitation of Xilinx SDx, and gives GPU developers the ability to easily migrate their OpenCL kernels to FPGA and achieve superior performance. Our results show that FOpenCL transformed OpenCL kernels can achieve significant speed-up on Xilinx SDx with reasonable overhead on hardware resources. We believe FOpenCL is the first flow that targets automatically migrating GPU OpenCL kernels to optimized FPGA OpenCL kernels.U of I OnlyAuthor requested U of Illinois access only (OA after 2yrs) in Vireo ETD syste