Memory access patterns and page promotion in hybrid memory systems

Hybrid heterogeneous memory systems are becoming increasingly popular as traditional memory systems are hitting performance and energy walls in processing data-intensive applications, which are becoming the norm with the resurgence of machine learning, big data, graph analytics, and database management systems, especially in modern datacenters. In addition to the massive data that these applications process, they exhibit varying and non-deterministic memory access patterns making I/O latency a prime criterion in the design considerations that go into building modern computing systems to support them. A traditional memory system moves data by swapping pages between the faster DRAM and the slower SSD. While applications with sequential accesses have better traffic between the DRAM and the SSD, applications with random page accesses, such as large graphs, often produce high traffic and exhibit little or no reuse of pages swapped into the DRAM. This thesis proposes a technique to identify memory access patterns, and a scalable and distributed technique to determine when pages should be promoted from the slower memory system to the faster memory system, thereby reducing I/O traffic. The proposed page promotion design shows up to 6.74x reduction in page traffic and 1.21x increase in the total hit rate of a data-intensive application with uniformly distributed random memory accesses