Architectural optimization for performance- and energy -constrained sensor processors.

Sensor processors and their applications are a growing area of focus in computer system research and design. Inherent to this design space is a reduced processing performance requirement. In addition, extremely high energy constraints are necessary such that sensor processors must execute low-performance tasks for long durations on small energy supplies. In this study, we demonstrate that subthreshold-voltage circuit design (400mV and below) lends itself well to the performance and energy demands of sensor processors. Moreover, we show that the landscape for microarchitectural energy optimization dramatically changes in the subthreshold domain. The dominance of leakage power in the subthreshold regime demands architectures that (i) reduce overall area and (ii) increase the utility of transistors while (iii) maintaining acceptable CPI efficiency. Moreover, we learn that memory comprises the single largest contributor to leakage energy, which makes high code density an essential requirement for sensor processor architectures. We confirm these observations by performing SPICE-level analysis of several sensor processor architectures. We further substantiate our concepts regarding subthreshold-voltage design by the fabrication and testing of a prototype chip. Based on the lessons learned form design space exploration, we propose an extremely energy-efficient sensor processor architecture by focusing on ISA, memory system design, and microarchitectural optimizations that reduce overall design size and improve energy-per-instruction. This design employs an ultra-compact 12-bit wide RISC instruction set architecture, which enables high code density via micro-operations and flexible operand modes. The design also features a unique memory architecture with a prefetch buffer and pre-decoded address bits, which permit both faster access to the memory and smaller instructions due to fewer address bits. It is capable of running at 142 kHz while consuming only 6000fJ/instruction, allowing the design to run continuously for 41 years on the energy stored in a 1g lithium-ion battery. Furthermore, in order to more accurately evaluate sensor processors, we introduce real-time, stream-oriented benchmark applications based on the common activities of sensor processors. Finally, we propose the use of three new evaluation metrics which capture the significant characteristics of a sensor processor: EPB (Energy Per Bundle), xRT (times Real-Time), and CFP (Composition Footprint).PhDApplied SciencesComputer scienceElectrical engineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/125721/2/3208521.pd