Potential of gallium arsenide and indium phosphide Gunn devices at high frequencies.

The purpose of this study is to investigate the capabilities of GaAs and InP Gunn devices at high frequencies. A three valley nonparabolic ensemble Monte Carlo model was developed to simulate the performance of Gunn devices with various cathode injectors. Initial characterization of triangular heterostructure barriers has shown them to be more efficient in transferring the electrons to the upper valleys when reverse biased. Good agreement with experimental results was obtained when quantum tunneling was included in the model. Oscillations were obtained around 180 GHz from a 1 $\mu$m GaAs conventional structure with a linearly graded doping in the active region. The effects of having a heterojunction cathode injector were investigated. Three types of injectors were considered: a forward biased triangular injector, a reverse biased triangular injector, and a rectangular injector. The reverse biased triangular barrier and the rectangular barrier were more efficient than the forward biased injector in reducing the dead zone. The advantages of these injectors include a smaller electric field at the anode and a smaller current density which improves the power capabilities. The main disadvantage consists of reducing the oscillation frequency for the same device length. A new method was developed for estimating the InP material parameters used in the Monte Carlo model by comparison with experimental results at high frequencies. Using these parameters, it was shown that 1 $\mu$m InP Gunn devices can be operated at frequencies in the D-band (110-170 GHz). Linearly graded doping profiles have been shown to result in better performance than flat doping profiles. More importantly, the thermal limitations are less severe than with flat doping profiles due to the smaller current density. A processing technology for GaAs and InP Gunn devices has been developed based on the integral heat sink process. Etch-stop layers between the substrate and the epilayers were included in the wafer design in order to completely remove the substrate and have better uniformity across the chip. InGaAs cap layers were used to reduce the contact resistance and the top contacts were gold plated to facilitate bonding.PhDApplied SciencesElectrical engineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/128885/2/9226933.pd