Boolean satisfiability has been successfully applied to various problems in electronic design automation. These applications typically involve targeting and solving a set of related satisfiability problems. However, there has been no attempt to take advantage of the similarity among the resulting satisfiability problems. In this thesis, we introduce the concept of incremental satisfiability and classify its manifestations in different problem domains into three classes. For each class, we present a method to efficiently solve the problem, followed by extensive experimental validation. We then apply the proposed incremental satisfiability engine to a number of applications in electronic design automation: timing analysis, delay fault test...
The satisfiability problem (SAT) is a fundamental problem in mathematical logic, constraint satisfac...
Abstract—Equivalence checking and property checking are powerful techniques to detect error traces. ...
This letter addresses the problem of delay fault test generation in circuits using macros whose impl...
Boolean satisfiability has been successfully applied to various problems in electronic design automa...
Boolean Satisfiability is a ubiquitous modeling tool in Electronic Design Automation (EDA). It finds...
This book provides an overview of automatic test pattern generation (ATPG) and introduces novel tech...
Recent advances in Boolean satisfiability have made it an attractive engine for solving many digital...
Recent advances in Boolean satisfiability have made it attractive to solve many digital VLSI design ...
Abstract — Testing constraints for real-time systems are usually verified through the satisfiability...
Automatic Test Pattern Generation (ATPG) is an important task to ensure that a chip functions correc...
A number of tasks in computer-aided analysis of combinational circuits, including test pattern gener...
This paper presents a novel approach to automate speedpath debugging taking into account variations....
The satisfiability problem (SAT) is a fundamental problem in mathematical logic, constraint satisfac...
Currently, Very Large Scale Integrated (VLSI) circuits and the resulting digital systems are widely ...
An Automatic Test Pattern Generator is an indispensable tool in the production of reliable computer ...
The satisfiability problem (SAT) is a fundamental problem in mathematical logic, constraint satisfac...
Abstract—Equivalence checking and property checking are powerful techniques to detect error traces. ...
This letter addresses the problem of delay fault test generation in circuits using macros whose impl...
Boolean satisfiability has been successfully applied to various problems in electronic design automa...
Boolean Satisfiability is a ubiquitous modeling tool in Electronic Design Automation (EDA). It finds...
This book provides an overview of automatic test pattern generation (ATPG) and introduces novel tech...
Recent advances in Boolean satisfiability have made it an attractive engine for solving many digital...
Recent advances in Boolean satisfiability have made it attractive to solve many digital VLSI design ...
Abstract — Testing constraints for real-time systems are usually verified through the satisfiability...
Automatic Test Pattern Generation (ATPG) is an important task to ensure that a chip functions correc...
A number of tasks in computer-aided analysis of combinational circuits, including test pattern gener...
This paper presents a novel approach to automate speedpath debugging taking into account variations....
The satisfiability problem (SAT) is a fundamental problem in mathematical logic, constraint satisfac...
Currently, Very Large Scale Integrated (VLSI) circuits and the resulting digital systems are widely ...
An Automatic Test Pattern Generator is an indispensable tool in the production of reliable computer ...
The satisfiability problem (SAT) is a fundamental problem in mathematical logic, constraint satisfac...
Abstract—Equivalence checking and property checking are powerful techniques to detect error traces. ...
This letter addresses the problem of delay fault test generation in circuits using macros whose impl...