Composite Cores: Improving Energy Efficiency Through Fine-Grained Heterogeneity.

From the smartphone to the data center, the world today demands computers that are both responsive and energy-efficient. While Moore’s law has continued to provide exponentially more transistors, increased power density has made it difficult to use all the transistors simultaneously. This limitation has forced architects to seek alternative designs that trade small increases in area for large gains in energy efficiency. Heterogeneous Multicore Systems (HMs) —comprising multiple cores with varying performance and energy characteristics—have emerged as a promising approach for improving energy efficiency while delivering high performance. HMs reduce energy consumption by identifying application phases and migrating execution to the most efficient core that meets performance requirements. However, migration requires tens of thousands of cycles, limiting their opportunities to coarse-graphed phases of hundreds of millions of instructions and reducing their potential to exploit energy-efficient cores. To address this, this thesis proposes bringing heterogeneity into the core itself by introducing Composite Cores, an architecture that pairs an high-performance Out-of-Order(OoO) backend and an energy-efficient In-Order (InO) backend that together achieve high performance and energy efficiency. By sharing architectural state between the backends, the migration overhead can be significantly reduced, enabling fine-grained migration and increasing the opportunities to utilize the InO backend without sacrificing performance. An intelligent controller migrates the application between backends to maximize energy efficiency while constraining performance loss. Together these innovations enable Composite Cores to save more energy without sacrificing performance. We further show that this design offers superior energy savings potential than Dynamic Voltage and Frequency Scaling. When pushing the migration intervals still further, pipeline draining and register transfer begin to pose intolerable levels of overhead. Therefore, this thesis proposes H-Pipes, an architecture that utilizes a shared register file to allow overlapped execution between backends. Finally, we equip the H-Pipes architecture with a scheduling system that incorporates both predictive and adaptive components to maximize the use of the more energy-efficient backend. Overall, this thesis provides a design for fine-grained heterogeneous architectures and offers novel hardware migration-control mechanisms. This design offers improved energy-saving benefits over current architectures.PHDComputer Science & EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/135925/1/lukefahr_1.pd