A quantitative approach to nonlinear IC process design rule scaling.

As minimum dimensions in integrated circuit technologies are reduced beyond 0.1 m m, linear process scaling becomes more difficult and costly. Exponentially rising manufacturing facility and process scaling costs can be better managed by performing nonlinear process shrinks. Nonlinear scaling allows the horizontal design rules to be reduced by different factors according to their ability to provide area and performance improvement in a cost effective manner. This thesis describes a methodology and CAD tools for use in selecting nonlinear design rule reduction ratios that make effective tradeoffs between die cost and performance. The cost effectiveness of nonlinear scaling is demonstrated for a complementary GaAs (CGaAsTM) process. CGaAs is a young technology with coarse design rules that would benefit significantly from a nonlinear shrink. The cost/benefit analysis for scaling the design rules is based on a process-independent optimizing SRAM compiler which was developed as part of this work. The methodology for nonlinear scaling includes identifying the rules which have the greatest impact on circuit area and analyzing the area and performance improvements as these rules are scaled through a range of practical scale factors. Benefit data (product of power and delay improvement ratios) is then combined with die cost estimates at each step to yield the cost/benefit ratio, a quantitative metric for design rule reduction. The slopes and inflection points of cost/benefit vs. scale factor plots guide process engineers in selecting reduction ratios for the various design rules. This procedure should be repeated, using the results of one pass as the starting point for the next. The cost/benefit analysis methodology compares embedded static RAMs that are generated by the PUMA process-independent SRAM compiler. This compiler, which is based on Duet's MasterPortTM layout compactor, can create optimized SRAM cell libraries for any complementary technology. It is capable of exploring a large design space, including the ability to adjust the transistors within the six-transistor memory cell. It produces power-delay curves that are combined with SRAM area measurements to provide the power, delay, and area data required for a cost/benefit analysis. A 0.5 m m CGaAs process is analyzed to demonstrate the methodology. A cost/benefit analysis of the design rules shows that the first scaling step should include a reduction of at least four rules: minimum transistor width, source/drain ohmic width, ohmic contact width, and active overlap of contact. The proportion by which these rules should be reduced depends on the number of wafers over which the scaling costs are amortized, and ranges from 20 to 40%. A similar analysis of the effect of transistor threshold voltage reduction clearly showed diminishing cost/benefit and cost/delay returns for an embedded SRAM.Ph.D.Applied SciencesElectrical engineeringMaterials scienceUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/131656/2/9929832.pd