High -level function and delay testing for digital circuits.

Conventional low-level (gate-level) testing methods are not well suited to circuits with modules whose implementation details are unknown, such as systems-on-a-chip (SOCs). SOCs extensively reuse large pre-designed and verified intellectual property JP) circuits, also known as cores, to shorten time-to-market. IP circuits are usually provided by third-party vendors, and their implementation details are often hidden from designers. Most existing SOC testing methods reuse pre-computed test sets for IP circuits, as well as design-for-test (DFT) techniques. However, for high-performance or high-density SOCs, the added area and performance overhead due to DFT circuits is not tolerable. On the other hand, high-level testing methods can generate tests from high-level (more abstract) descriptions of EP circuits, and apply the tests without the DFT circuits needed for test set reuse. In this dissertation, we propose a high-level testing approach for both function and delay faults to address SOC testing problems. Two new high-level fault models, the coupling fault (CF) model and the coupling delay fault (CDF) model, are introduced. The corresponding test sets are defined and related to other low- and high-level test sets. It is shown that (reduced) coupling test sets are smaller than the so-called universal test sets, but still achieve very high stuck-at fault coverage for a broad range of implementations. The coupling delay test set we propose is smaller than other existing high-level delay test sets, and detects all robust path delay faults in any realization of the target function. A high-level delay test generation method for modular circuits is developed to reduce test set size. Experimental results are presented which demonstrate that significant reduction in test set size can be achieved by taking advantage of circuit hierarchy. A small but powerful high-level robust delay test set is derived from the coupling delay test set using dominance relationships. The application of robust coupling delay test sets to modular circuits provides better coverage of delay faults. Our experiments confirm that significant reduction in test set size can be achieved by using the new test set instead of the coupling delay test set.PhDApplied SciencesComputer scienceElectrical engineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/123318/2/3068998.pd