Block RAM implementation of a reconfigurable real-time PID controller

Despite the numerous advantages reconfigurable computing adds to a system, it is only advantageous if the execution time exceeds the configuration time. As a result of the long configuration time, reconfiguration is only suitable for quasi-static applications. Due to the additional overhead required for communication, the bus-based architectures most commonly used to connect the configuration controller to the memory contribute to the configuration time. A method proposed to ameliorate this overhead is an architecture utilizing localized block RAM (BRAM), directly connected to the configuration controller to store the configuration data. The drawback of this method is that the BRAM is extremely limited and only a discrete set of configurations can be stored. This paper is a work in progress and proposes a hardware reconfiguration architecture that addresses the size limitation of the localized BRAM-architecture by using parameterizable configuration. This will allow a single bitstream stored in the BRAM to be specialized according to certain parameters, which will be used to reconfigure the device. This will migrate reconfigurable computing to more dynamic applications. The architecture proposed in this paper will be validated using real-time PID control of a five degree of freedom active magnetic bearing syste