Silicon Bottom Cell for III-V/Si Multi-junction Solar Cells

This thesis looks at optimising the silicon sub-cell in a III-V on Silicon multi-junction solar cell, with the results providing a pathway for high efficiency devices in the near future. Whilst III-V/Si multi-junction solar cells are recognised as a potential pathway to devices with efficiencies well above the limits for conventional silicon devices a number of challenges remain. Amongst these are the need to design for a truncated incident spectrum and the impact of the III-V/silicon interface, optical path length enhancement realisation, and the negative impacts on silicon performance of the III-V/silicon integration process. A numerical simulation model for the silicon sub-cell was developed to analyse the performance of current champion efficiency devices. It was found that a shallower emitter junction improves performance and the III-V/silicon interface must be considered when designing the silicon sub-cell. The model was extended to investigate, for the first time, a rear junction sub-cell design and a heterojunction with intrinsic thin layer (HIT) rear surface design, respectively. Results suggest the HIT approach holds the greatest promise for high performance in the future. The silicon minority carrier lifetime degradation with III-V integration thermal processes, reported by a number of groups, was also investigated. Results have shown two factors that can lead to this degradation, firstly, the presence of thermally activated grown-in defects, and secondly, the diffusion of metal impurities during high temperature processes. A process was developed consisting of a 1000 degree Celcius anneal under oxygen flow plus the deposition of a silicon nitride layer at the rear of the substrate which was proven to prevent lifetime degradation under typical thermal processing experienced during the III-V/silicon integration. Finally, a novel external surface texture scheme, manufactured using textured silicon and rose petals to imprint PDMS layers was developed. This additive layer was used to improve the optical performance of both wafer bonded and monolithic epitaxial III-V/silicon cells, with increases in short circuit current of 0.95 and 0.49 mA/cm2 respectively. The use of these layers sees the efficiency for the wafer bonded device increase by 2 % absolute, whilst for the monolithic device the increase was 0.65 % absolute