Design of a dedicated IFT microcontroller

The design of a Dedicated IFT Microcontroller originated from the successful implementation of the Iterative Feedback Tuning (IFT) technique into the Digital Signal Processor microcontroller (DSP56F807C) at the University of Cape Town in 2006. However, implementation of the IFT technique on a general-purpose microcontroller is neither optimal, nor a cost-effective exercise, as most of the microcontroller peripherals remain unused, and drain energy for doing nothing. In addition, microcontrollers and DSPs are software-driven devices whose nature is sequential in executing algorithms, and hence have a significant effect on the bandwidth of the closed-loop control. To mitigate the said problem, the design of a Dedicated IFT Microcontroller is proposed in this thesis. To accomplish this goal, the preliminary task was to explore the IFT theory and its applications, followed by a review of the literature on FPGA design methodology for industrial control systems, Microcontroller design principles, and FPGA theory and trends. Furthermore, a survey of electronic design automation (EDA) tools and other application software was also conducted. After the literature review, the IFT was investigated exhaustively by applying it to three types of plants, namely: a DC motor, an oscillatory plant, and an unstable plant. Each of these plants were tested using three types of initial controllers, namely heavilydamped, critically damped and under-damped initial controllers. The plants were also tested by varying the amplitude of the reference signal, followed by using a single-step signal of constant amplitude of one volt. The intention of exploring all of these possibilities was meant to firmly expose the IFT boundaries of applicability, so that the final product would not be vulnerable to unnecessary post-production discoveries. The design methodology adopted in this research was a popular hierarchical and modular top-down procedure, which is an array of abstraction levels that are detailed as: system level, behavioural level, Register-Transfer Level (RTL) and Gate level. At system level, the Dedicated IFT Microcontroller was defined. Thereafter, at behavioural level, the design was simulated using VHDL, created by porting the LabView IFT code to the Xilinx EDA tool. At the RTL, the synthesisable VHDL code utilising fixed-point number representation was written. The compiled bit file was downloaded onto National Instruments (NI) Digital Electronics FPGA Board featuring iii the Spartan 3 series FPGA. This was tested, using a method known as simulation in the hardware. The key contribution of this thesis is the experimental validation of the IFT technique on FPGA hardware as it has never been published before, the work described in chapter four and five. The other contribution is the analysis of 1DOF IFT technique in terms of limitations of applicability for correct implementation, which is the main work of chapter three. This work could be used to explore other computational methods, like the use of floating-point number representation for high resolution and accuracy in numerical computations. Another avenue that could be exploited is Xilinx's recent Vivado methodology, which has the capacity for traditional programming languages like C or C++, as these have in-built floating-point number capability. Finally, out of this work, two papers have already been published by Springer and IEEE Xplore Publishers, and a journal paper has also been written for publication in the Control Systems Technology journal