Effect of top gate bias on NBIS in dual gate a-IGZO TFTs

We report the effects of top gate bias (VTG) on negative bias illumination stress (NBIS) applied at bottom gate terminal in dual gate amorphous indium gallium zinc oxide (a-IGZO) thin film transistor (TFT), while transfer characteristics measured at bottom gate terminal before and after stress. NBIS in a-IGZO TFTs show negative transfer shift due to the formation of positive charges, likely ionization of oxygen vacancies (VO → VO+/VO2+) and/or hole traps in Gate insulator/a-IGZO interface and a-IGZO bulk. We observed -3.26V shift after NBIS, for -10V bias at VTG, which decreases to -1.3V for VTG = +10V. It clearly revels the formation of less defects in IGZO channel when the Fermi level is shifted upward by positive top gate bias