Add to ORKGAn explanation for the observed variations in the output behaviour of SOI transistors with different buried oxide thicknesses is presented. At low drain bias, the temperature effects are relatively insignificant while at high drain bias, the temperature effects dominate the nonlinear behaviour of the output characteristics
High temperature effects on the impact ionization of the n-channel fully depleted (FD) SOI MOSFET ar...
In this work, the effect of rise in temperature from 25 ∘ C to 175 ∘ C on the performance of 22-nm f...
Operation of fully depleted inversion mode SOI n-MOSFET, fabricated on UNIBOND wafers, in wide range...
This paper presents the influence of the drain bias and gate length of partially depleted SOI MOSFET...
This paper presents a new approach to optimize the RF performance at high temperatures for low power...
At zero-temperature-coefficient bias points, transistors are known to have stable DC performance wit...
In this paper, the temperature dependence of transistor fabricated in a thin film deep submicron SOI...
Abstract—The temperature dependence of high-frequency noise characteristics for deep-submicrometer b...
This work investigates the possibility to tune the zero-temperature-coefficient (ZTC) points in part...
Conventional bulk silicon CMOS circuits can operate only at moderate temperatures (up to 150-200°C)....
The gate characteristics (ID-VGS) of fully depleted, lightly doped, enhanced SOI n-MOSFET are simula...
683-688The temperature dependence of threshold voltage and drain-source current of thin film SOI M...
Thin-film SOI MOSFETs are known to have superior device properties for hightemperature applications,...
This work studies the influence of the back gate voltage on the LDD SOI nMOSFETs series resistance a...
Measurements of accumulation-mode (AM) MOS SOI transistors in the 150-300-degrees-C temperature rang...
High temperature effects on the impact ionization of the n-channel fully depleted (FD) SOI MOSFET ar...
In this work, the effect of rise in temperature from 25 ∘ C to 175 ∘ C on the performance of 22-nm f...
Operation of fully depleted inversion mode SOI n-MOSFET, fabricated on UNIBOND wafers, in wide range...
This paper presents the influence of the drain bias and gate length of partially depleted SOI MOSFET...
This paper presents a new approach to optimize the RF performance at high temperatures for low power...
At zero-temperature-coefficient bias points, transistors are known to have stable DC performance wit...
In this paper, the temperature dependence of transistor fabricated in a thin film deep submicron SOI...
Abstract—The temperature dependence of high-frequency noise characteristics for deep-submicrometer b...
This work investigates the possibility to tune the zero-temperature-coefficient (ZTC) points in part...
Conventional bulk silicon CMOS circuits can operate only at moderate temperatures (up to 150-200°C)....
The gate characteristics (ID-VGS) of fully depleted, lightly doped, enhanced SOI n-MOSFET are simula...
683-688The temperature dependence of threshold voltage and drain-source current of thin film SOI M...
Thin-film SOI MOSFETs are known to have superior device properties for hightemperature applications,...
This work studies the influence of the back gate voltage on the LDD SOI nMOSFETs series resistance a...
Measurements of accumulation-mode (AM) MOS SOI transistors in the 150-300-degrees-C temperature rang...
High temperature effects on the impact ionization of the n-channel fully depleted (FD) SOI MOSFET ar...
In this work, the effect of rise in temperature from 25 ∘ C to 175 ∘ C on the performance of 22-nm f...
Operation of fully depleted inversion mode SOI n-MOSFET, fabricated on UNIBOND wafers, in wide range...