Continuous-time Pipelined Binary-search Flash ADC

A novel ADC architecture is introduced with a sampling rate comparable to flash converters, but with reduced input capacitance, power consumption and kickback. Broadband active delay circuits pass the input along with a clock through a continuous-time pipeline. The 5-bit prototype has a 2.5-bit first stage, 1.5-bit second stage, and 2-bit final stage allowing for digital correction of interstage errors. Consuming 47mW at 7GS/s in 28nm CMOS, the converter has 15fF differential input capacitanceM.A.S