This paper considers a hybrid memory system composed of memory technologies with different characteristics; in particular a small, near memory exhibiting high bandwidth, i.e., 3D-stacked DRAM, and a larger, far memory offering capacity at lower bandwidth, i.e., off-chip DRAM. In the past,the near memory of such a system has been used either as a DRAM cache or as part of a flat address space combined with a migration mechanism. Caches and migration offer different tradeoffs (between performance, main memory capacity, data transfer costs, etc.) and share similar challenges related todata-transfer granularity and metadata management. This paper proposes Hybrid2 , a new hybrid memory system architecture that combines a DRAM cache with a migrati...
“©2014 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for a...
This dissertation mainly addresses two problems that emerge along with the 'big data' trend: the inc...
The number of concurrently executing processes and their memory demand in multi-core systems continu...
The bandwidth of traditional DRAM is pin limited and so does not scale wellwith the increasing deman...
Although 3D-stacked DRAM offers substantially higher bandwidth than commodity DDR DIMMs, it cannot y...
<p>Hybrid main memories composed of DRAM as a cache to scalable non-volatile memories such as phase-...
Cache memories have been usually implemented with Static Random-Access Memory (SRAM) technology sin...
DRAM has long been the preferred technology choice for main memory. With new challenges of high ene...
Caching techniques have been an efficient mechanism for mitigating the effects of the processor-memo...
Memory systems containing different types of memory with varying capacity, latency, and bandwidth ar...
As device technologies scale in the nanometer era, the current off-chip DRAM technologies are very c...
As technology scales down, energy consumption is becoming a big problem for traditional SRAM-based c...
Non-volatile memories (NVMs) have aroused vast interest in hybrid memory systems due to their promis...
To sustain processor performance, demand for memory capacity and bandwidth continues to grow. Comput...
With the imminent slowing down of DRAM scaling, Phase Change Memory (PCM) is emerging as a lead alte...
“©2014 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for a...
This dissertation mainly addresses two problems that emerge along with the 'big data' trend: the inc...
The number of concurrently executing processes and their memory demand in multi-core systems continu...
The bandwidth of traditional DRAM is pin limited and so does not scale wellwith the increasing deman...
Although 3D-stacked DRAM offers substantially higher bandwidth than commodity DDR DIMMs, it cannot y...
<p>Hybrid main memories composed of DRAM as a cache to scalable non-volatile memories such as phase-...
Cache memories have been usually implemented with Static Random-Access Memory (SRAM) technology sin...
DRAM has long been the preferred technology choice for main memory. With new challenges of high ene...
Caching techniques have been an efficient mechanism for mitigating the effects of the processor-memo...
Memory systems containing different types of memory with varying capacity, latency, and bandwidth ar...
As device technologies scale in the nanometer era, the current off-chip DRAM technologies are very c...
As technology scales down, energy consumption is becoming a big problem for traditional SRAM-based c...
Non-volatile memories (NVMs) have aroused vast interest in hybrid memory systems due to their promis...
To sustain processor performance, demand for memory capacity and bandwidth continues to grow. Comput...
With the imminent slowing down of DRAM scaling, Phase Change Memory (PCM) is emerging as a lead alte...
“©2014 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for a...
This dissertation mainly addresses two problems that emerge along with the 'big data' trend: the inc...
The number of concurrently executing processes and their memory demand in multi-core systems continu...