Frequency synthesizer design for 60 GHz wireless communication

The wireless communications technologies are now deeply involved in varies of Internet of Thing (IoT) envolutions and applications. The prospective implementations of these technologies are all based on tranceiver chips, at the heart of which, a radio-frequency (RF) frequency synthesizer is essential to generate required local oscilation frequency. And the demanding features of wide frequency range, agile response, low power consumption and programmability make the design of the frequency synthesizer a real challenge. To meet the requirements for 60GHz wireless communication based on IEEE 802.11ad, a phase-locked loop frequency synthesizer is designed in a 55nm CMOS process. After reviewing wireless communication based on IEEE 802.11ad, the frequency plan is proposed and the architecture of the frequency synthesizer is determined. Focusing on the LC voltage-controlled oscillator (VCO), loop bandwidth regulation, the integer-N PLL-based frequency synthesizer is researched in this dissertation, and the detailed achievements are as follows: After introduction, the basic theory of the phase-locked loop (PLL) is recaptured, and both the integer-N PLL and fractional-N modulation are covered, impacts of which on the loop transient response and phase noise are discussed, followed by the introduction of the loop bandwidth variation and possible compensation. In order to reduce the VCO phase noise, switched capacitor array are adopted to design a wideband VCO with low VCO gain (K_VCO). VCO frequency sub-band interval (f_step) is minimized and the overlap is maximized to narrow the possible tunable voltage range for necessary frequency, which helps to alleviate the operating range requirement of the charge pump (CP). A resistor is adopted instead of MOS current source at the tail to avoid its noise contribution. And an LC resonator is inserted between the tail resistor and cross-coupled MOS pair to further reduce the phase noise. This VCO is implemented in a 55nm CMOS technology, and the simulation results show that it covers the frequency range of 18.6 ~ 23.6GHz, with K_VCO of -120 ~ -283MHz/V and f_step of 25.2 ~ 45.1MHz, and the phase noise of -105.4@1MHz and -128.1@10MHz, respectively. To mitigate the variations of loop performances at different frequencies, the programmable charge pump (CP) is employed to regulate the loop characteristics across the entire frequency range. In order to accelerate the frequency shifting, the division-ratio-based direct mapping pre-caliberation is proposed before traditional counter-based AFC. The further calibration is introduced using a quarter of VCO output frequency which improves the AFC efficiency. This AFC reduces the calibration time significantly. As far as the previous analysis and design are considered, a 20GHz integer-N PLL frequency synthesizer is implemented in a CMOS 55nm 1P9M technology. Simulation results show that the frequency synthesizer covers the frequency range of 18.6 ~ 23.6GHz by employing the proposed LC VCO design, attaining the carrier frequencies of 19.44GHz, 20.16GHz, 20.88GHz, and 21.60GHz. Loop BW is regulated to be 284 ~ 286kHz (0.7% relative variation), and the typical PN at 21.60GHz is around -94.5dBc/Hz@10kHz, -105.4@1MHz, and -128.1@10MHz, respectively, while consuming 28.43mW under 1.2V power supply. The final design meets the specifications.Master of Science (Electronics