Single Event Effects (SEE) Mitigation of Reconfigurable FPGAs

This paper discusses the application of Space Micro‘s Time-Triple Modular Redundancy (TTMR™) and Hardened-Core (H-Core™) technologies for mitigation of Single Event Effects in Xilinx Virtex-II field programmable gate arrays (FPGA). TTMR is the application of time and spatial redundancy for mitigating Single Event Upsets (SEU). H-Core is an auxiliary rad-hard chip used for mitigating Single Event Functional Interrupts (SEFI). These technologies have been proven to perform in proton radiation environments and are presently the driving force behind our powerful rad-hard computers built from COTS processors. These same technologies with a few modifications have been applied to mitigate SEUs, configuration upsets, and SEFIs in Virtex-II FPGAs. The application of TTMR and H-Core2 has been successfully demonstrated to mitigate SEUs and SEFIs under radiation. The target system has been named the Proton300k™. The Proton300k is an ideal reconfigurable computing platform for radiation hardened, high performance data processing at low cost and outperforms similar systems built from expensive rad-hard electronics (from rad-hard processes)