Towards a Twofold Approach to the Verification of Generated VHDL Systems

The rise of Model Driven Development, Domain Specific Languages and Generative Programming as new techniques for systems and software engineering means that the actual code that is compiled and executed is no longer written by a human, it is generated by a tool. To give confidence that the desired system has been generated, it is necessary to provide a successful means to verify the generated code. This paper proposes a twofold approach to verification, drawing on techniques from both the testing and formal approaches to verification. The concepts are discussed in the context of generating VHDL code from a UML State Machine