Generating Simulators From Multi-Level Coordinated Specifications

Computer system simulations are one of the hardware and software designer\u27s most useful tools, especially when dealing with embedded and novel computer systems. They allow users to run programs on and obtain information about any platform, whether or not it exists in the real world. However, many simulators lack the flexibility to adapt to new requirements and design considerations, especially if they simulate multiple levels of detail across the hardware-software interface. Adjustments made to the instruction set of a target architecture must be manually tied into the micro-architecture, and vice versa, hobbling design space exploration and re-enforcing the stagnation of instruction sets. This dissertation addresses this issue by making three contributions: (1) a new methodology, known as CoGs, for creating simulators by generating them from multiple related specification languages; (2) CASL, a language for specifying modern micro-architectures; and (3) CSIP, a set of CASL patterns for describing the interplay between static and dynamic CASL elements that simplifies tying instructions to micro-architectural elements. CISL and CASL, the languages used in CoGs, each describe the semantics of a computer system at a different level of detail, but share a common semantic core that can be used as a basis of comparison. CoGs generates a simulator from the specifications by using a sophisticated matching process to blend behavioral, structural, and timing information at a fine-grained level. The resulting blended simulator accurately captures timing metrics but relies on functional simulation constructs such as decode trees and detailed behavior when appropriate, all with minimal user intervention. We evaluated the system by generating two blended simulators: one combining the MIPS32 instruction set architecture (ISA) with a DLX processor specification, and one combining the PowerPC ISA with an MPC processor. We also tested its flexibility by adding the SmartMIPS extension to the MIPS32 ISA, and evaluating different alternatives for implementing the underlying micro-architecture