This work presents a novel run-time reconfiguration model. It uses multiple configuration controllers instead of only one in traditional devices. The configuration SRAM is divided into several individual sections, and controllers can reconfigure different sections in parallel. Therefore, multiple tasks can be loaded simultaneously. Two static task schedulers are developed to evaluate the device. Already with two controllers, the overall configuration overhead can be reduced by about 40% using non-prefetch scheduling. When using prefetch scheduling, another 16.2% reduction can be achieved on average of all results
In the single machine environment, several schedul-ing algorithms exist that allow to quantify sched...
Dynamically reconfigurable hardware is a promising technology that combines in the same device both ...
International audienceThis paper deals with the real-time scheduling in a reconfigurable multi-core ...
This work presents a novel run-time reconfiguration model. It uses multiple configuration controller...
Multitasking on reconfigurable logic can achieve very high silicon reusability. However, configurati...
Dynamically reconfigurable hardware (DRHW) not only has high silicon reusability, but it can also de...
Run-time reconfigurable logic is an interesting design alterative in SoC design because it can simul...
Summarization: Partial reconfiguration suffers from the inherent high latency and low throughput whi...
Aim of this paper is to define a scheduling of the task graph of an application that minimizes its t...
In this paper, we present a novel solution to the problem of configuration management for multi-cont...
Summarization: Partial reconfiguration (PR) of FPGAs can be used to dynamically extend and adapt the...
Runtime reconfigurable systems built upon devices with partial reconfiguration can provide reduction...
Run-time reconfigurable logic is a very attractive alterative in the design of SoC. However, configu...
Summarization: Partial reconfiguration (PR) of FPGAs can be used to dynamically extend and adapt the...
In this paper, an approach that uses dynamic voltage scaling (DVS) to reduce the configuration energ...
In the single machine environment, several schedul-ing algorithms exist that allow to quantify sched...
Dynamically reconfigurable hardware is a promising technology that combines in the same device both ...
International audienceThis paper deals with the real-time scheduling in a reconfigurable multi-core ...
This work presents a novel run-time reconfiguration model. It uses multiple configuration controller...
Multitasking on reconfigurable logic can achieve very high silicon reusability. However, configurati...
Dynamically reconfigurable hardware (DRHW) not only has high silicon reusability, but it can also de...
Run-time reconfigurable logic is an interesting design alterative in SoC design because it can simul...
Summarization: Partial reconfiguration suffers from the inherent high latency and low throughput whi...
Aim of this paper is to define a scheduling of the task graph of an application that minimizes its t...
In this paper, we present a novel solution to the problem of configuration management for multi-cont...
Summarization: Partial reconfiguration (PR) of FPGAs can be used to dynamically extend and adapt the...
Runtime reconfigurable systems built upon devices with partial reconfiguration can provide reduction...
Run-time reconfigurable logic is a very attractive alterative in the design of SoC. However, configu...
Summarization: Partial reconfiguration (PR) of FPGAs can be used to dynamically extend and adapt the...
In this paper, an approach that uses dynamic voltage scaling (DVS) to reduce the configuration energ...
In the single machine environment, several schedul-ing algorithms exist that allow to quantify sched...
Dynamically reconfigurable hardware is a promising technology that combines in the same device both ...
International audienceThis paper deals with the real-time scheduling in a reconfigurable multi-core ...