A Square Root Algorithm Based on FPGA

随着嵌入式等实时系统技术的发展,越来越多的数字信号处理要求将开平方等运算用硬件实现.本文介绍了一种改进的不恢复余数的开平方算法,分析了它的一些优点,用VHDL语言在Xilinx公司的FPGA器件上实现了该算法;分别设计了被开方数是16位和8位的电路,并进行了比较.实验结果表明,与其他算法比较,改进的不恢复余数的开平方算法具有输出延时小和占用资源少的优点,同时随着被开方数的增加,最高频率下降幅度不大,具有较好的实用价值.With the development of embedded real time systems,more and more application areas need hardware implementation of square root algorithm.This paper introduced a revised non-restoring square root algorithm,discussed it's advantages and implementation way on FPGA.Different circuit was designed separately when radicand is 16 bits and 8 bits,respectively.The experiment shows that the algorithm introduced here has many advantages in terms on practical performance,such as output delay and speed.In the mean time with the increasing of the number of radicand,the maximum frequency only decreased a few.厦门大学预研基金(Y07014)资