Challenges of accurate gate length characterization with emphasis on the effects of intra-die thermal variation

For state-of-the-art semiconductor technologies, it is challenging to predict the performance and characteristics of an integrated circuit chip based on FET parameters measured from test structures placed outside the chip due to process variation induced intra-die variation of FET parameters. It is shown how intra-die gate length variation itself can cause significant variation in FET characteristics, stressing the need for accurate measurement of gate length. It is also discussed how significant intra-die thermal absorption variation is caused by non-optimized rapid thermal anneal (RTA) conditions. This variation is dependent on the ramp rate of the anneal tool and depends on local pattern density of various types of exposed layers of the wafer. It is shown that this variation can even create errors in the measurement of key Metal Oxide Semiconductor Field Effect Transistor (MOSFET) parameters like gate length and gate capacitance from test structures. Different electrical methods for measuring gate length will be discussed, namely, the resistive technique, where the resistance of the nominal poly-silicon line is normalized to a long-wide resistor; and the capacitive technique, where the capacitance of the nominal poly-silicon line is normalized to that of a long-wide plate gate capacitor. It is shown, for the first time, that the capacitive technique of gate length measurement is more immune to errors introduced by rapid thermal anneal (RTA) driven intra-die thermal absorption variation than resistive techniques. This is because, thermal anneal driven intra-die gate capacitance variation is much less than the sheet resistance variation. Methods of minimizing these measurement errors are briefly discussed