Performance-Driven Hierarchical Design and Management of Networks-on-Chip in Many-Core System

As on-chip interconnection network scales to integrate more processing elements, physical limitations have threatened the scalibility and performance of many-core systems. Currently, Networks-on-Chip have replaced the bus and crossbar methods and been the prevalent many-core architecture because of the flexible scalibility and low cost. In NoCs with ever-growing core count, requests from distant cores generate long range traffic, and the long range traffic has jeopardized the system performance in the format of increasing the end-to-end latency significantly. Though researchers have discovered that almost of the traffic is from nearby nodes, the small portion of the communication between distant nodes consumes most of the network bandwidth. In order to facilitate the NoC communication efficiency, we propose a hierarchical mesh NoC with multiple mesh layers added on a regular 2D mesh base. Deterministic hierarchical routing is implemented to generate shorter routing paths for long range traffic. However, the proposed approaches create a congestion challenge because of uneven traffic distribution among levels. We further introduce a dynamic management scheme to leverage the hierarchy more efficiently. The proposed NoC and management approaches are simulated with Garnet simulator. The results show that our design can produce lower average network latency and higher throughput that translates to faster communication processing