Design and implementation of a power efficient data-aware SRAM Array

In this project, two new power efficient data-aware cells have been proposed. In the proposed cells, dynamic power consumption is reduced by reducing the voltage swing on the respective bit-lines during write operation. In first proposed cell (7T BLC), an extra transistor is included in one of the pull down path of the 6T cell. This transistor is known as a tail transistor and its switching activity is controlled by the voltage at the bit-line. The second cell (9T cell) is designed after modifying the conventional 6T cell at the architecture level. The switching operation of the pull up and pull down transistors of the left inverter is controlled by an additional write signal. The value of the write signal is decided by the data to be written in the cell. The cell behaves dynamically during write operation due to a broken latch which allows the data to be flipped quickly. The read operation in the 9T cell is performed on a separate circuit which consists of two series connected transistors and one read bit-line