A size-adaptive time-step algorithm for accurate simulation of aging in analog ICs

Paper presented at the 2017 IEEE International Symposium on Circuits and Systems (ISCAS), held in Baltimore, MD, USA, on 28-31 May 2017.Variability is one of the main and critical challenges introduced by the continuous scaling in integrated technologies and the need for reliable ICs. In this regard, it is necessary to take into account time-zero (i.e., spatial or process variability) and time-dependent variability (i.e., aging). While process variability has been extensively treated, considerable efforts are currently being made to develop new simulation tools to evaluate the impact of aging, but very few works have been focused on reliability simulation for analog ICs. The models for the wear-out phenomena typically use the stress conditions of the analog circuit during its normal operation. However, many of the available solutions often miss the bi-directional link between stress and biasing and their changes over time and, therefore, accuracy losses occur while evaluating the impact of aging in the circuit performance. This paper proposes a new size-adaptive time-step algorithm to efficiently update the stress conditions in the reliability simulation of analog ICs. Compared to similar solutions, the work presented here is able to attain similar accuracy levels with lower CPU times