Level-1 track finding with an all-FPGA system at CMS for the HL-LHC

The CMS experiment at the LHC is designed to study a wide range of high energy physics phenomena. It employs a large all-silicon tracker within a 3.8 T magnetic solenoid, which allows precise measurements of transverse momentum ( $p_T$ ) and vertex position. This tracking detector will be upgraded to coincide with the installation of the High-Luminosity LHC (HL-LHC), which will provide up to about 10$^{35}$ cm$^{-2}$ s$^{-1}$ to CMS, or up to 200 collisions per 25 ns bunch crossing. This new tracker must maintain the nominal physics performance in this more challenging environment. Novel tracking modules that utilize closely spaced silicon sensors to discriminate on track $p_T$ have been developed to allow the readout of only hits compatible with $p_T$ > 2-3 GeV tracks to off-detector trigger electronics. This would enable the use of tracking information to produce the Level-1 trigger of the experiment, a requirement to keep the Level-1 triggering rate below the 750 kHz target, while maintaining physics sensitivity. A concept for an all-FPGA based track finder using a fully time-multiplexed architecture is presented. Hardware demonstrators have been used to prove the feasibility and capability of such a system using two different reconstruction algorithms. The proposed scaling of the demonstrators to the final system is showed as well as the new technologies used in the first prototypes