International audienceThis paper presents a technique for precise crosstalk delay measurement based on on-chip sampling. Results obtained on a test chip fabricated in 0.7-/spl mu/m CMOS technology exhibit a 100% delay increase in a long coupled line configuration
We present a methodology for on-chip characterization of the pin-to-pin propagation delay of single ...
This paper presents a novel analytical closed form expression for the crosstalk noise voltage and de...
We present a technique for an all-digital on-chip delay measurement system to measure the skews in a...
International audienceThis paper describes a specific technique for measuring and characterizing the...
UnrestrictedThis dissertation investigates the effect of capacitive crosstalk on interconnect and lo...
Due to technology scaling and increasing clock frequency, problems due to noise effects lead to an i...
International audienceAdvances in interconnect technologies, such as the increase in the number of m...
This thesis is about a design for diagnosis (DFD) technique for bus wires. It uses digital method to...
Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Com...
Abstract—The impact of crosstalk effects on timing performance is increasing as the device geometrie...
[[abstract]]Increased noise/interference effects, such as crosstalk, power supply noise, substrate n...
The increased noise/interference effects, such as crosstalk, power supply noise, substrate noise and...
Abstract — As the device geometries are shrinking, the impact of crosstalk effects increases, which ...
Abstract—On-chip parasitic inductance inherent to the power distribution network has becoming signif...
During the last few years, new synchronization tech-niques to send data between IC’s at increasingly...
We present a methodology for on-chip characterization of the pin-to-pin propagation delay of single ...
This paper presents a novel analytical closed form expression for the crosstalk noise voltage and de...
We present a technique for an all-digital on-chip delay measurement system to measure the skews in a...
International audienceThis paper describes a specific technique for measuring and characterizing the...
UnrestrictedThis dissertation investigates the effect of capacitive crosstalk on interconnect and lo...
Due to technology scaling and increasing clock frequency, problems due to noise effects lead to an i...
International audienceAdvances in interconnect technologies, such as the increase in the number of m...
This thesis is about a design for diagnosis (DFD) technique for bus wires. It uses digital method to...
Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Com...
Abstract—The impact of crosstalk effects on timing performance is increasing as the device geometrie...
[[abstract]]Increased noise/interference effects, such as crosstalk, power supply noise, substrate n...
The increased noise/interference effects, such as crosstalk, power supply noise, substrate noise and...
Abstract — As the device geometries are shrinking, the impact of crosstalk effects increases, which ...
Abstract—On-chip parasitic inductance inherent to the power distribution network has becoming signif...
During the last few years, new synchronization tech-niques to send data between IC’s at increasingly...
We present a methodology for on-chip characterization of the pin-to-pin propagation delay of single ...
This paper presents a novel analytical closed form expression for the crosstalk noise voltage and de...
We present a technique for an all-digital on-chip delay measurement system to measure the skews in a...
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