This article presents a software protection technique against radiation-induced faults which is based on a multi-threaded strategy. Data triplication and instructions flow duplication or triplication techniques are used to improve system reliability and thus, ensure a correct system operation. To achieve this objective, a relaxed lockstep model to synchronize the execution of both, redundant threads and variables under protection on different processing units is defined. The evaluation was performed by means of simulated fault injection campaigns in a multi-core ARM system. Results show that despite being considered techniques that imply an evident overhead in memory and instructions (Duplication With Comparison and Re-Execution – DWC-R and...
The use of Commercial Off-The-Shelf (COTS) processors is increasingly attractive for the space domai...
As technology scaling increases computer memory’s bit-cell density and reduces the voltage of semico...
This paper presents a novel methodology for the HW/SW co-design of fault tolerant embedded systems t...
Soft errors are one of the significant design technology challenges at smaller technology nodes and ...
Comunicación presentada en the 11th European Conference on Radiation and its Effects on Components a...
ARM processors are leaders in embedded systems, delivering high-performance computing, power efficie...
This work presents the evaluation of a new dualcore lockstep hybrid approach aimed to improve the fa...
This article presents Lock-V, a heterogeneous fault tolerance architecture that explores a dual-core...
All-Programmable System-on-Chips (APSoCs) constitute a compelling option for employing applications ...
The embedded processors operating in safety- or mission-critical systems are not allowed to fail. An...
Commercial off-the-shelf microprocessors are the core of low-cost embedded systems due to their prog...
Due to technology scaling, which means reduced transistor size, higher density, lower voltage and mo...
The main objective of this thesis is to develop techniques that can beused to analyze and mitigate t...
As MOS device sizes continue shrinking, lower charges, for example those charges carried by single i...
In the last decade the dominance of the general computing systems market has being replaced by embed...
The use of Commercial Off-The-Shelf (COTS) processors is increasingly attractive for the space domai...
As technology scaling increases computer memory’s bit-cell density and reduces the voltage of semico...
This paper presents a novel methodology for the HW/SW co-design of fault tolerant embedded systems t...
Soft errors are one of the significant design technology challenges at smaller technology nodes and ...
Comunicación presentada en the 11th European Conference on Radiation and its Effects on Components a...
ARM processors are leaders in embedded systems, delivering high-performance computing, power efficie...
This work presents the evaluation of a new dualcore lockstep hybrid approach aimed to improve the fa...
This article presents Lock-V, a heterogeneous fault tolerance architecture that explores a dual-core...
All-Programmable System-on-Chips (APSoCs) constitute a compelling option for employing applications ...
The embedded processors operating in safety- or mission-critical systems are not allowed to fail. An...
Commercial off-the-shelf microprocessors are the core of low-cost embedded systems due to their prog...
Due to technology scaling, which means reduced transistor size, higher density, lower voltage and mo...
The main objective of this thesis is to develop techniques that can beused to analyze and mitigate t...
As MOS device sizes continue shrinking, lower charges, for example those charges carried by single i...
In the last decade the dominance of the general computing systems market has being replaced by embed...
The use of Commercial Off-The-Shelf (COTS) processors is increasingly attractive for the space domai...
As technology scaling increases computer memory’s bit-cell density and reduces the voltage of semico...
This paper presents a novel methodology for the HW/SW co-design of fault tolerant embedded systems t...